MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 34

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

READ STATUS 70h
Table 11:
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
SR
Bit
0
1
2
3
4
5
6
7
1
4
Write protect
Ready/busy
Ready/busy
Program
Pass/fail
Page
Status Register Bit Definition
–
–
–
–
Notes: 1. Status register bit 0 reports a “1” if a TWO-PLANE PROGRAM or TWO-PLANE BLOCK ERASE
Program Page
Pass/fail (N -1)
Cache Mode
Write protect
Ready/busy
Pass/fail (N)
Ready/busy
cache
NAND Flash devices have an 8-bit status register that the software can read during
device operation. Table 11 describes the status register.
After a READ STATUS (70h) command, all READ cycles are from the status register until a
new command is given. Changes in the status register are seen on I/O[7:0] as long as CE#
and RE# are LOW; it is not necessary to start a new READ cycle to see these changes.
In devices that have more than one die sharing a common CE# pin, the READ STATUS
(70h) command reports the status of the die that was last addressed. During interleaved
die operations, the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command must
be used to select the die that should report status. In this situation, using the READ STA-
TUS (70h) command will result in bus contention, as both die will respond until the next
operation is issued.
While monitoring the status register to determine when the transfer from the Flash array
to the data register (
make the change from STATUS to DATA. After the READ command has been re-issued,
pulsing the RE# line will result in outputting data, starting from the initial column
address.
2. Status register bit 5 is “0” during the actual programming operation. If cache mode is
3. Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follows bit 6
4. Status register bit 7 typically mirrors the status of the WP# pin. However, when the OTP
–
–
–
operation fails on one or both planes. Status register bit 1 reports a “1” if a TWO-PLANE
PROGRAM PAGE CACHE MODE operation fails on one or both planes. Use TWO-
PLANE/MULTIPLE-DIE READ STATUS (78h) to determine the plane on which the operation
failed.
used, this bit will be “1” when all internal operations are complete.
(see Figure 20 on page 37 and Figure 23 on page 40).
PROGRAM DATA command is used, status register bit 7 returns “0” if the OTP area is pro-
tected. This bit is not modified until the next PROGRAM or ERASE command is issued.
3
2
Write protect Write protect
Page Read
Ready/busy
Ready/busy
Micron Confidential and Proprietary
–
–
–
–
–
t
R) is complete, the user must re-issue the READ (00h) command to
Cache Mode
Ready/busy
Page Read
Ready/busy
cache
34
–
–
–
–
–
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3
2
16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Write protect 0 = Protected
Block Erase
Ready/busy
Ready/busy
Pass/fail
–
–
–
–
0 = Successful PROGRAM/ERASE
1 = Error in PROGRAM/ERASE
0 = Successful PROGRAM
1 = Error in PROGRAM
0
0
0
0 = Busy
1 = Ready
0 = Busy
1 = Ready
1 = Not protected
Command Definitions
©2005 Micron Technology, Inc. All rights reserved.
Definition
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