MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 35

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

Figure 19:
PAGE READ CACHE MODE Operations
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16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
Status Register Operation for READ STATUS
Micron NAND Flash devices have a cache register that can be used to increase READ
operation speed. Data can be output from the device's cache register while concurrently
moving a page from the NAND Flash array to the data register.
To begin a PAGE READ CACHE MODE sequence, begin by reading a page from the
NAND Flash array to the cache register using the PAGE READ (00h-30h) command (see
“PAGE READ 00h-30h” on page 24). R/B# goes LOW during
= 00). After
commands:
• PAGE READ CACHE MODE SEQUENTIAL (31h) command to begin copying the next
• PAGE READ CACHE MODE RANDOM (00h-31h) command to begin copying the page
After the PAGE READ CACHE MODE SEQUENTIAL or PAGE READ CACHE MODE RAN-
DOM command has been issued, R/B# goes LOW (status register bits 6 and 5 = 00) for
t
R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the cache register is
available and that a page is being copied from the NAND Flash array to the data register.
At this point data can be output from the cache register, beginning at column address 0,
by toggling RE#. The RANDOM DATA READ (05h-E0h) command can be used to change
the column address of the data being output by the device.
After outputting the desired number of bytes from the cache register, it is possible to
either begin an additional PAGE READ CACHE MODE (31h or 00h-31h) operation or
issue the PAGE READ CACHE MODE LAST (3Fh) command.
If an additional PAGE READ CACHE MODE (31h or 00h-31h) command is issued, R/B#
goes LOW (status register bits 6 and 5 = 00) for
ied to the cache register, then the next page begins copying into the data register. After
t
cache register is available and that the specified page is copying from the NAND Flash
array to the data register. At this point data can be output from the cache register, begin-
ning at column address 0, by toggling RE#. The RANDOM DATA READ (05h-E0h) com-
mand can be used to change the column address of the data being output by the device.
If the PAGE READ CACHE MODE LAST (3Fh) command is issued, R/B# goes LOW (status
register bits 6 and 5 = 00) for
register. After
DCBSYR1 while the next page begins copying into the data register. After
DCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the
WE#
I/Ox
CE#
RE#
CLE
sequential page from the NAND Flash array to the data register
specified in this command from the NAND Flash array to the data register.
t
R (R/B# is HIGH and status register bits 6 and 5 = 11), issue either of these
t
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DCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 11, indicating
70h
t
DCBSYR2 while the data register is copied into the cache
35
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16, 32, 64, 128Gb NAND Flash Memory
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t CLR
t
DCBSYR2 while the data register is cop-
t REA
t
Command Definitions
R (status register bits 6 and 5
Status output
©2005 Micron Technology, Inc. All rights reserved.
t
DCBSYR1,
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