MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 121

IC MPU 32BIT COLDF 90MHZ 208FQFP

MCF5307AI90B

Manufacturer Part Number
MCF5307AI90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307AI90B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Maximum Clock Frequency
90 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
90MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
FQFP
Program Memory Size
8KB
Cpu Speed
90MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Table 4-5 describes ACRn fields.
Reset
31–24
23–16
15
14–13
12–7
6–5
4–3
2
1–0
Field
I
R/W
Bits
Rc
31
Address
Address
Name
mask
base
CM
W
E
S
Address Base
The SIM MBAR region should be mapped as cache-inhibited
through an ACR.
Address base. Compared with address bits A[31:24]. Eligible addresses that match are
assigned the access control attributes of this register.
Address mask. Setting a mask bit causes the corresponding address base bit to be ignored.
The low-order mask bits can be set to define contiguous regions larger than 16 Mbytes. The
mask can define multiple noncontiguous regions of memory.
Enable. Enables or disables the other ACRn bits.
0 Access control attributes disabled
1 Access control attributes enabled
Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this
address range or if the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
Reserved; should be cleared.
Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are
described in Section 4.9.2, “Cache-Inhibited Accesses.”
00 Cacheable, write-through
01 Cacheable, copyback
10 Cache-inhibited, precise
11 Cache-inhibited, imprecise
Reserved, should be cleared.
Write protect. Selects the write privilege of the memory region.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
Figure 4-9. Access Control Register Format (ACRn)
Uninitialized
Freescale Semiconductor, Inc.
24 23
For More Information On This Product,
Table 4-5. ACRn Field Descriptions
Address Mask
Chapter 4. Local Memory
Go to: www.freescale.com
Write (R/W by debug module)
ACR0: 0x004; ACR1: 0x005
NOTE:
16 15 14 13 12
Description
E
0
S
Uninitialized
7
6
CM
Cache Registers
5
4
3
W
2
4-23
1
0

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