MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 228

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chip-Select Operation
10.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See
Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).” Figure 10-1 shows
the correspondence between data byte lanes and the external chip-select memory. Note that
all lanes are driven, although unused lines are undefined.
10.3.1.2 Global Chip-Select Operation
CS0, the global (boot) chip select, allows address decoding for boot ROM before system
initialization. Its operation differs from other external chip-select outputs after system reset.
After system reset, CS0 is asserted for every external access. No other chip-select can be
used until the valid bit, CSMR0[V], is set, at which point CS0 functions as configured and
CS[7:1] can be used. At reset, the port size and automatic acknowledge functions of the
global chip-select are determined by the logic levels of the inputs on D[7:5]. Table 10-4 and
Table 10-5list the various reset encodings for the configuration signals multiplexed with
D[7:5].
Provided the required address range is in the chip-select address register (CSAR0), CS0 can
10-4
Figure 10-1. Connections for External Memory Port Sizes
Table 10-4. D7/AA, Automatic Acknowledge of Boot CS0
Table 10-5. D[6:5]/PS[1:0], Port Size of Boot CS0
32-bit port
16-bit port
Freescale Semiconductor, Inc.
8-bit port
data bus
External
memory
memory
memory
D[6:5]/PS[1:0]
For More Information On This Product,
D7/AA
0
1
00
01
1x
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MCF5307 User’s Manual
D[31:24]
Byte 0
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
Disabled
Enable with 15 wait states
BE0
Boot CS0 AA Configuration at Reset
D[23:16]
Byte 1
Byte 1
Byte 3
BE1
Boot CS0 Port Size at Reset
Driven, undefined
D[15:8]
Byte 2
Driven, undefined
32-bit port
16-bit port
8-bit port
BE2
Byte 3
D[7:0]
BE3