MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 285

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.4.2 Destination Address Registers (DAR0–DAR3)
For dual-address transfers only, DARn, Figure 12-5, holds the address to which the DMA
controller sends data.
12.4.3 Byte Count Registers (BCR0–BCR3)
BCRn, Figure 12-6 and Figure 12-7, holds the number of bytes yet to be transferred for a
given block.The offset within the memory map is based on the value of
MPARK[BCR24BIT]. BCRn decrements on the successful completion of the address
transfer of either a write transfer in dual-address mode or any transfer in single-address
mode. BCRn decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses,
respectively.
Figure 12-6 shows BCR for BCR24BIT = 1.
Figure 12-7 shows BCR for BCR24BIT = 0.
Address
Address
Reset
Reset
Field
Field
R/W
R/W
31
31
Figure 12-6. Byte Count Registers (BCRn)—BCR24BIT = 1
On-chip DMAs do not maintain coherency with MCF5307
caches and so must not transfer data to cacheable memory.
—
—
Figure 12-5. Destination Address Registers (DARn)
Freescale Semiconductor, Inc.
For More Information On This Product,
24 23
Chapter 12. DMA Controller Module
0000_0000_0000_0000_0000_0000_0000_0000
Go to: www.freescale.com
MBAR + 0x30C, 0x34C, 0x38C, 0x3AC
MBAR + 304, 0x344, 0x384, 0x3C4
NOTE:
0000_0000_0000_0000_0000_0000
DAR
R/W
R/W
DMA Controller Module Programming Model
BCR
12-7
0
0