MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 327

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The interrupt level, priority, and auto-vectoring capability is programmed in SIM register
ICR4 for UART0 and ICR5 for UART1. See Section 9.2.1, “Interrupt Control Registers
(ICR0–ICR9).”
Note that the UARTs can also automatically transfer data by using the DMA rather than
interrupting the core. When UIMR[FFULL] is 1 and a receiver’s FIFO is full, it can send
an interrupt to a DMA channel so the FIFO data can be transferred to memory. Note also
that UART0 and UART1’s interrupt requests are connected to DMA channel 2 and
channel 3, respectively.
Table 14-13 briefly describes the UART module signals.
Figure 14-18 shows a signal configuration for a UART/RS-232 interface.
Transmitter
Serial Data
Output (TxD)
Receiver
Serial Data
Input (RxD)
Clear-to-
Send (CTS)
Request-to-
Send (RTS)
Signal
TxD is held high (mark condition) when the transmitter is disabled, idle, or operating in the local
loop-back mode. Data is shifted out on TxD on the falling edge of the clock source, with the least
significant bit (lsb) sent first.
Data received on RxD is sampled on the rising edge of the clock source, with the lsb received first.
This input can generate an interrupt on a change of state.
This output can be programmed to be negated or asserted automatically by either the receiver or the
transmitter. When connected to a transmitter’s CTS, RTS can control serial data flow.
The terms ‘assertion’ and ‘negation’ are used to avoid
confusion between active-low and active-high signals.
‘Asserted’ indicates that a signal is active, independent of the
voltage level; ‘negated’ indicates that a signal is inactive.
Freescale Semiconductor, Inc.
Figure 14-18. UART/RS-232 Interface
For More Information On This Product,
Table 14-13. UART Module Signals
UART
CTS
RTS
RxD
TxD
Chapter 14. UART Modules
Go to: www.freescale.com
NOTE:
Description
RS-232 Transceiver
DI2
DO2
DI1
DO1
UART Module Signal Definitions
14-17