MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 141

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 5-9 describes DBR fields.
Table 5-10 describes DBMR fields.
The DBR supports both aligned and misaligned references. Table 5-11 shows relationships
between processor address, access size, and location within the 32-bit data bus.
5.4.6 Program Counter Breakpoint/Mask Registers
The PC breakpoint register (PBR) defines an instruction address for use as part of the
trigger. This register’s contents are compared with the processor’s program counter register
when TDR is configured appropriately. PBR bits are masked by clearing corresponding
PBMR bits. Results are compared with the processor’s program counter register, as defined
in TDR. Figure 5-10 shows the PC breakpoint register.
31–0
31–0
Bits
Bits
Mask
Data
Name
Name
(PBR, PBMR)
Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows
the corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus.
Setting a DBMR bit causes that bit to be ignored.
Table 5-11. Access Size and Operand Data Location
Freescale Semiconductor, Inc.
Table 5-10. DBMR Field Descriptions
For More Information On This Product,
A[1:0]
Table 5-9. DBR Field Descriptions
00
01
10
11
0x
1x
xx
Chapter 5. Debug Support
Go to: www.freescale.com
Access Size
Longword
Word
Word
Byte
Byte
Byte
Byte
Description
Description
Operand Location
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
D[7:0]
Programming Model
5-13