MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 255

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 11-13 describes DACRn fields.
31–18
17–16
15
14
13–12
11
10–8
7
Bit
Name
CASL CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with
CBM
Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode)
BA
RE
—
—
—
—
Base address register. With DCMR[BAM], determines the address range in which the associated
DRAM block is located. Each BA bit is compared with the corresponding address of the current bus
cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the
same as in asynchronous operation.
Reserved, should be cleared.
Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM
block.
0 Do not refresh associated DRAM block
1 Refresh associated DRAM block
Reserved, should be cleared.
manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature:
Reserved, should be cleared.
Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and
bank select lines to correspond to different addresses, these resources are programmable. CBM
determines the addresses onto which these functions are multiplexed.
CBM
000
001
010
011
100
101
110
111
This encoding and the address multiplexing scheme handle common SDRAM organizations. Bank
select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits.
Reserved, should be cleared.
t
t
t
t
t
command
t
RCD
CASL
RAS
RP
RWL
EP
—Last data out to precharge command)
—Precharge command to
—
—SRAS assertion to SCAS assertion
,
—SCAS assertion to data out
t
Command Bit
17
18
19
20
21
22
23
24
RDL
ACTV
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
—Last data input to precharge
Freescale Semiconductor, Inc.
command to precharge command
For More Information On This Product,
Parameter
Bank Select Bits
18 and up
19 and up
20 and up
21 and up
22 and up
23 and up
24 and up
25 and up
Go to: www.freescale.com
ACTV
command
Description
CASL= 00 CASL = 01 CASL= 10 CASL= 11
1
1
2
1
1
1
Number of Bus Clocks
2
2
4
2
1
1
Synchronous Operation
3
3
6
3
1
1
3
3
6
3
1
1
11-21