MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 320

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Descriptions
6–4
3–2
14-10
Bits
Value
000
001
010
011
100
101
110
111
00
01
10
11
NO COMMAND
RESET MODE
REGISTER POINTER
RESET RECEIVER
RESET
TRANSMITTER
RESET ERROR
STATUS
RESET BREAK
CHANGE INTERRUPT
START BREAK
STOP BREAK
NO ACTION TAKEN
TRANSMITTER
ENABLE
TRANSMITTER
DISABLE
Command
Table 14-6. UCRn Field Descriptions (Continued)
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Causes the mode register pointer to point to UMR1n.
Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes
the receiver FIFO pointer. No other registers are altered. Because it places the
receiver in a known state, use this command instead of
reconfiguring the receiver.
are altered. Because it places the transmitter in a known state, use this
command instead of
lears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after a
data block is received.
Clears the delta break bit, UISRn[DB].
Forces TxD low. If the transmitter is empty, the break may be delayed up to one
bit time. If the transmitter is active, the break starts when character transmission
completes. The break is delayed until any character in the transmitter shift
register is sent. Any character in the transmitter holding register is sent after the
break. The transmitter must be enabled for the command to be accepted. This
command ignores the state of CTS.
Causes TxD to go high (mark) within two bit times. Any characters in the
transmitter buffer are sent.
Causes the transmitter to stay in its current mode: if the transmitter is enabled, it
remains enabled; if the transmitter is disabled, it remains disabled.
Enables operation of the channel’s transmitter. USRn[TxEMP,TxRDY] are set. If
the transmitter is already enabled, this command has no effect.
Terminates transmitter operation and clears USRn[TxEMP,TxRDY]. If a character
is being sent when the transmitter is disabled, transmission completes before the
transmitter becomes inactive. If the transmitter is already disabled, the command
has no effect.
Reserved, do not use.
MISC Field (This field selects a single command.)
disables the transmitter and clears USRn[TxEMP,TxRDY]. No other registers
TC Field (This field selects a single command)
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MCF5307 User’s Manual
TRANSMITTER DISABLE
Description
when reconfiguring the transmitter.
RECEIVER DISABLE
when