MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 324

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Descriptions
14.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn)
The UDUn registers (formerly called UBG1n) holds the MSB, and the UDLn registers
(formerly UBG2n) hold the LSB of the preload value. UDUn and UDLn concatenate to
provide a divider to BCLKO for transmitter/receiver operation, as described in
Section 14.5.1.2.1, “BCLKO Baud Rates.”
14-14
Bits
6–3
Address
Address
7
2
1
0
Reset
Reset
Field
Field
R/W
R/W
COS
—
DB
FFULL/
RxRDY
TxRDY
Name
7
7
Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt.
Reserved, should be cleared.
Delta break.
0 No new break-change condition to report. Section 14.3.5, “UART Command Registers (UCRn),”
1 The receiver detected the beginning or end of a received break.
RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if UMR1n[FFULL/RxRDY]
= 1. Duplicate of USRn[FFULL/RxRDY]. If FFULL is enabled for UART0 or UART1, DMA channels 2
or 3 are respectively interrupted when the FIFO is full.
Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters
1 The transmitter holding register is empty and ready to be loaded with a character.
The minimum value that can be loaded on the concatenation of
UDUn with UDLn is 0x0002. Both UDUn and UDLn are
write-only and cannot be read by the CPU.
describes the
loaded into the transmitter holding register when TxRDY = 0 are not sent.
Figure 14-12. UART Divider Upper Register (UDUn)
Figure 14-13. UART Divider Lower Register (UDLn)
Table 14-9. UISRn/UIMRn Field Descriptions
Freescale Semiconductor, Inc.
RESET BREAK
For More Information On This Product,
Go to: www.freescale.com
MBAR + 0x1D8 (UDU0), 0x218 (UDU1)
MBAR + 0x1DC (UDL0), 0x21C (UDL1)
MCF5307 User’s Manual
-
CHANGE INTERRUPT
NOTE:
Divider MSB
Divider LSB
0000_0000
0000_0000
Description
R/W
R/W
command.
0
0