MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 381

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.7.3 DRAM Write (DRAMW)
The DRAM write signal (DRAMW) is asserted to signify that a DRAM write cycle is
underway. A read bus cycle is indicated by the negation of DRAMW.
17.7.4 Synchronous DRAM Column Address Strobe (SCAS)
The synchronous DRAM column address strobe (SCAS) is registered during synchronous
mode to route directly to the SCAS signal of SDRAMs.
17.7.5 Synchronous DRAM Row Address Strobe (SRAS)
The synchronous DRAM row address strobe output (SRAS) is registered during
synchronous mode to route directly to the SRAS signal of external SDRAMs.
17.7.6 Synchronous DRAM Clock Enable (SCKE)
The synchronous DRAM clock enable output (SCKE) is registered during synchronous
mode to route directly to the SCKE signal of external SDRAMs. This signal provides the
clock enable to the SDRAM.
17.7.7 Synchronous Edge Select (EDGESEL)
The synchronous edge select input (EDGESEL) helps select additional output hold times
for signals that interface to external SDRAMs. It provides the following three modes of
operation for SDRAM control signals:
17.8 DMA Controller Module Signals
The DMA controller module uses the signals in the following subsections to provide
external request for either a source or destination.
• When EDGESEL is tied high, SDRAM control signals change on the rising edge of
• When EDGESEL is tied low, SDRAM control signals change on the falling edge of
• When EDGESEL is tied to the external clock (normally buffered BCLKO), which
BCLKO.
BCLKO.
drives the SDRAM and other devices, SDRAM signals are generated within the
MCF5307 make a transition on the rising edge of the SDRAM clock. See
Figure 11-14 on page 11-19. This loop-back configuration provides additional
output hold time for MCF5307 interface signals provided to the SDRAM. In this
case, the SDRAM clock operates at the BCLKO frequency, with a possible slight
phase delay.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 17. Signal Descriptions
Go to: www.freescale.com
DMA Controller Module Signals
17-17