MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 336

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Operation
Features of this local loop-back mode are as follows:
14.5.3.3 Remote Loop-Back Mode
In remote loop-back mode, shown in Figure 14-25, the channel automatically transmits
received data bit by bit on the TxD output. The local CPU-to-transmitter link is disabled.
This mode is useful in testing receiver and transmitter operation of a remote channel. For
this mode, the transmitter uses the receiver clock.
Because the receiver is not active, received data cannot be read by the CPU and error status
conditions are inactive. Received parity is not checked and is not recalculated for
transmission. Stop bits are sent as they are received. A received break is echoed as received
until the next valid start bit is detected.
14.5.4 Multidrop Mode
Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or
multiprocessor applications. In this mode, a master can transmit an address character
followed by a block of data characters targeted for one of up to 256 slave stations.
Although slave stations have their channel receivers disabled, they continuously monitor
the master’s data stream. When the master sends an address character, the slave receiver
channel notifies its respective CPU by setting USRn[RxRDY] and generating an interrupt
(if programmed to do so). Each slave station CPU then compares the received address to its
station address and enables its receiver if it wishes to receive the subsequent data characters
or block of data from the master station. Slave stations not addressed continue monitoring
the data stream. Data fields in the data stream are separated by an address character. After
14-26
• Transmitter and CPU-to-receiver communications continue normally in this mode.
• RxD input data is ignored
• TxD is held marking
• The receiver is clocked by the transmitter clock. The transmitter must be enabled,
but the receiver need not be.
CPU
CPU
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 14-25. Remote Loop-Back
Disabled
Disabled
Figure 14-24. Local Loop-Back
Go to: www.freescale.com
MCF5307 User’s Manual
Rx
Tx
Rx
Tx
Disabled
Disabled
Disabled
Disabled
RxD Input
TxD Input
RxD Input
TxD Input