MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 125

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Read
miss
Read hit
Write
miss
(copy-
back)
Write
miss
(write-
through)
Write hit
(copy-
back)
Write hit
(write-
through)
Cache
invalidate
Cache
push
Access
(C,W)I1 Read line from
(C,W)I2 Not possible.
CI3
WI3
CI4
WI4
(C,W)I5 No action;
(C,W)I6
(C,W)I7
Invalid (V = 0)
memory and update
cache;
supply data to
processor;
go to valid state.
Read line from
memory and update
cache;
write data to cache;
go to modified state.
Write data to
memory;
stay in invalid state.
Not possible.
Not possible.
stay in invalid state.
No action;
stay in invalid state.
Freescale Semiconductor, Inc.
Table 4-6. Cache Line State Transitions
For More Information On This Product,
Chapter 4. Local Memory
Go to: www.freescale.com
(C,W)V1 Read new line from
(C,W)V2 Supply data to processor;
CV3
WV3
CV4
WV4
(C,W)V5 No action;
(C,W)V6 No action;
(C,W)V7 No action;
Valid (V = 1, M = 0)
memory and update
cache;
supply data to processor;
stay in valid state.
stay in valid state.
Read new line from
memory and update
cache;
write data to cache;
go to modified state.
Write data to memory;
stay in valid state.
Write data to cache;
go to modified state.
Write data to memory and
to cache;
stay in valid state.
go to invalid state.
go to invalid state.
stay in valid state.
Current State
WD3 Write data to memory;
WD4 Write data to memory and
CD1 Push modified line to
CD2 Supply data to processor;
CD3 Push modified line to
CD4 Write data to cache;
CD5 No action (modified data
CD6 Push modified line to
CD7 Push modified line to
Cache Operation Summary
Modified (V = 1, M = 1)
buffer;
read new line from memory
and update cache;
supply data to processor;
write push buffer contents
to memory;
go to valid state.
stay in modified state.
buffer;
read new line from memory
and update cache;
write push buffer contents
to memory;
stay in modified state.
stay in modified state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[CINVA] before
switching modes.
stay in modified state.
to cache;
go to valid state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[CINVA] before
switching modes.
lost);
go to invalid state.
memory;
go to invalid state.
memory;
go to valid state.
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