MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 415

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In Figure 18-28, the external device is master during C1 and C2. It releases bus control in
C3 by asserting BG to the MCF5307. During C4 and C5, the MCF5307 is implicit master
because no internal access is pending. In C5, an internal bus request becomes pending,
causing the MCF5307 to become explicit bus master in C6 by asserting BD. In C7, the
external device removes the bus grant to the MCF5307. The MCF5307 does not release the
bus (the MCF5307 continues to assert BD) until the transfer ends.
Chapter 5, “Debug Support is a MCF5307 bus arbitration state diagram. States are
described in Table 18-6.
SIZ[1:0], TM[2:0]
A[31:0], TT[1:0]
BCLKO
Figure 18-28. Two-Wire Implicit and Explicit Bus Mastership
D[31:0]
The MCF5307 can start a transfer in the clock cycle after BG
is asserted. The external master must not assert BG to the
MCF5307 while driving the bus or the part may be damaged.
R/W
TIP
BG
BD
TS
AS
TA
C1
Freescale Semiconductor, Inc.
External Master
For More Information On This Product,
C2
Chapter 18. Bus Operation
Go to: www.freescale.com
C3
NOTE:
C4
Mastership
Implicit
General Operation of External Master Transfers
C5
C6
MCF5307
C7
Mastership
Explicit
C8
C9
18-27