MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 230

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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15–0
Chip-Select Registers
10.4.1 Chip-Select Module Registers
The chip-select module is programmed through the chip select address registers
(CSAR0–CSAR7), chip select mask registers (CSMR0–CSMR7), and the chip select
control registers (CSCR0–CSCR7).
10.4.1.1 Chip-Select Address Registers (CSAR0–CSAR7)
Chip select address registers, Figure 10-2, specify the chip select base addresses.
Table 10-7 describes CSAR[BA].
10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7)
The chip select mask registers, Figure 10-3, are used to specify the address mask and
allowable access types for the respective chip selects.
Bits
10-6
0x0DC
MBAR
Offset
0x0D8
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to
these reserved address spaces and reserved register bits have no effect.
Name
BA
Figure 10-2. Chip Select Address Registers (CSAR0–CSAR7)
Base address. Defines the base address for memory dedicated to chip select CS[7:0]. BA is compared
to bits 31–16 on the internal address bus to determine if chip-select memory is being accessed.
Reset
External masters cannot access MCF5307 on-chip memories or
MBAR, but can access any of the chip-select module registers.
Field
Addr
R/W
[31:24]
15
Table 10-6. Chip-Select Registers (Continued)
0x0B0 (CSAR4); 0x0BC (CSAR5); 0x0C8 (CSAR6); 0x0D4 (CSAR7)
0x080 (CSAR0); 0x08C (CSAR1); 0x098 (CSAR2); 0x0A4 (CSAR3);
Freescale Semiconductor, Inc.
Table 10-7. CSARn Field Description
For More Information On This Product,
Reserved
Chip-select mask register—bank 7 (CSMR7) [p. 10-6]
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1
MCF5307 User’s Manual
[23:16]
NOTE:
Uninitialized
R/W
Description
BA
Chip-select control register—bank 7
[15:8]
(CSCR7) [p. 10-8]
0
[7:0]