MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 127

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In the current state is modified.
4.13 Cache Initialization Code
The following example sets up the cache for FLASH or ROM space only.
Read miss
Read hit
Write miss
(copyback)
Write miss
(write-through)
Write hit
(copyback)
Write hit
(write-through)
Cache invalidate
Cache push
Cache push
Access
move.l#0x81000300,D0 //enable cache, invalidate it,
movecD0, CACR
move.l #0xFF00C000,D0//cache FLASH space, enable,
movecD0,ACR0
Table 4-9. Cache Line State Transitions (Current State Modified)
WD3 Write data to memory;
WD4 Write data to memory and to cache;
CD1 Push modified line to buffer;
CD2 Supply data to processor;
CD3 Push modified line to buffer;
CD4 Write data to cache;
CD5 No action (modified data lost);
CD6 Push modified line to memory;
CD7 Push modified line to memory;
read new line from memory and update cache;
supply data to processor;
write push buffer contents to memory;
go to valid state.
stay in modified state.
read new line from memory and update cache;
write push buffer contents to memory;
stay in modified state.
stay in modified state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[CINVA] before switching modes.
stay in modified state.
go to valid state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[CINVA] before switching modes.
go to invalid state.
go to invalid state.
go to valid state.
Freescale Semiconductor, Inc.
For More Information On This Product,
//default mode is cache-inhibited imprecise
//ignore FC2, cacheable, writethrough
Chapter 4. Local Memory
Go to: www.freescale.com
Response
Cache Initialization Code
4-29