MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 409

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If the MCF5307 is the only possible master, BG can be tied to GND—no arbiter is needed.
18.8.1 Bus Arbitration Signals
Bus arbitration signal timings in Table 18-7 are referenced to the system clock, which is not
considered a bus signal. Clock routing is expected to meet application requirements.
18.9 General Operation of External Master Transfers
An external master asserts its hold signal (such as HOLDREQ) when it executes a bus
cycle, driving BG high and forcing the MCF5307 to hold all bus requests. During an
external master cycle, the MCF5307 can provide memory control signals (OE, CS[7:0],
BE/BWE[3:0], RAS[1:0], CAS[3:0]) and TA while the external master drives the address
and data bus and other required bus control signals. When the external master asserts TS or
AS to the MCF5307, the beginning of a bus cycle is identified and the MCF5307 starts
decoding the address driven.
Explicit
master
External
master
Signal
State
BR
BG
BD
I/O
MCF5307
O
O
External
I
Master
Table 18-6. MCF5307 Arbitration Protocol States (Continued)
Bus request. Indicates to an external arbiter that the processor needs to become bus master. BR is
negated when the MCF5307 begins an access to the external bus with no other internal accesses
pending. BR remains negated until another internal request occurs.
Bus grant. An external arbiter asserts BG to indicate that the MCF5307 can control the bus at the
next rising edge of BCLKO. When the arbiter negates BG, the MCF5307 must release the bus as
soon as the current transfer completes. The external arbiter must not grant the bus to any other
device until both BD and BG are negated.
Bus driven. The MCF5307 asserts BD to indicate it is current master and is driving the bus. If it loses
bus mastership during a transfer, it completes the last transfer of the current access, negates BD,
and three-states all bus signals on the rising edge of BCLKO. If it loses mastership during an idle
clock cycle, it three-states all bus signals on the rising edge of BCLKO.
Table 18-7. ColdFire Bus Arbitration Signal Summary
Driven Asserted The MCF5307 is explicit bus master when BG is asserted and at least
driven
Bus
Not
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Negated An external device is bus master (BG negated to MCF5307). The
For More Information On This Product,
BD
Chapter 18. Bus Operation
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one bus cycle has been initiated. It asserts BD and retains explicit
mastership until BG is negated even if no active bus cycles are executed.
It releases the bus at the end of the current bus cycle, then negates BD
and three-states the bus signals.
MCF5307 can assert OE, CS[7:0], BE/BWE[3:0], TA, and all DRAM
controller signals (RAS[1:0], CAS[3:0], SRAS, SCAS, DRAMW, SCKE).
Description
General Operation of External Master Transfers
Description
18-21