MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 123

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The following CACR loads assume the default cache mode is copyback.
CacheLoadAndLock:
The following code preloads half of the cache (4 Kbytes). It assumes a contiguous block of
data is to be mapped into the cache, starting at a 0-modulo-4K address.
CacheLoop:
; A 4K region has been loaded into levels 0 and 1 of the 8K cache. lock it!
4.12 Cache Operation Summary
This section gives operational details for the cache and presents cache-line state diagrams.
4.12.1 Cache State Transitions
Using the V and M bits, the cache supports a line-based protocol allowing individual cache
lines to be invalid, valid, or modified. To maintain memory coherency, the cache supports
both write-through and copyback modes, specified by the corresponding ACR[CM], or
CACR[DCM] if no ACR matches.
Read or write misses to copyback regions cause the cache controller to read a cache line
from memory into the cache. If available, tag and data from memory update an invalid line
in the selected set. The line state then changes from invalid to valid by setting the V bit. If
all lines in the row are already valid or modified, the pseudo-round-robin replacement
algorithm selects one of the four lines and replaces the tag and data. Before replacement,
modified lines are temporarily buffered and later copied back to memory after the new line
has been read from memory.
move.l
cmpi.l
bne
rts
move.l
movec
move.l
lea
tst.b
lea
subq.l
bne.b
move.l
movec
rts
align
#0xA1000100,d0; enable and invalidate cache ...
d0,cacr ; ... in the CACR
#256,d0
data_,a0
(a0)
16(a0),a0
#1,d0
CacheLoop
#0xA8000100,d0
d0,cacr
16
Freescale Semiconductor, Inc.
For More Information On This Product,
d0,a0
#4,d0
setloop
Chapter 4. Local Memory
Go to: www.freescale.com
;256 16-byte lines in 4K space
; load pointer defining data area
;touch location + load into data cache
;increment address to next line
;decrement loop counter
;if done, then exit, else continue
;set the cache lock bit ...
; ... in the CACR
;set = 0, way = d0
;flushed all the ways?
Cache Operation Summary
4-25