MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 323

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 14-8 describes UACRn fields.
14.3.10 UART Interrupt Status/Mask Registers
The UART interrupt status registers (UISRn), Figure 14-11, provide status for all potential
interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and
UIMRn bits are set, the internal interrupt output is asserted. If a UIMRn bit is cleared, the
state of the corresponding UISRn bit has no effect on the output.
Table 14-9 describes UISRn and UIMRn fields.
7–1
0
Address
Address
Bits
Reset
Reset
Field
Field
R/W
R/W
Name
IEC
(UISRn/UIMRn)
—
Figure 14-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
COS
7
7
Reserved, should be cleared.
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external
True status is provided in the UISRn regardless of UIMRn
settings. UISRn is cleared when the UART module is reset.
transition on the CTS input (if UIMRn[COS] = 1).
Figure 14-10. UART Auxiliary Control Register (UACRn)
MBAR + 0x1D4 (UISR0), 0x214 (UISR1); MBAR + 0x1D4 (UIMR0), 0x214 (UIMR1)
6
Freescale Semiconductor, Inc.
Table 14-8. UACRn Field Descriptions
For More Information On This Product,
Chapter 14. UART Modules
MBAR + 0x1D0 (UACR0), 0x210 (UACR1)
Read only for status, write only for mask.
Go to: www.freescale.com
—
NOTE:
—
0000_0000
0000_0000
Write only
Description
3
DB
2
FFULL/RxRDY
Register Descriptions
1
1
TxRDY
IEC
0
0
14-13