MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 227

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Each CSn can assert during specific CPU space accesses such as interrupt-acknowledge
cycles and each can be accessed by an external master. CS0 is a global chip select after reset
and provides relocatable boot ROM capability.
10.3.1 General Chip-Select Operation
When a bus cycle is initiated, the MCF5307 first compares its address with the base address
and mask configurations programmed for chip selects 0–7 (configured in CSCR0–CSCR7)
and DRAM block 0 and 1 address and control registers (configured in DACR0 and
DACR1). If the driven address matches a programmed chip select or DRAM block, the
appropriate chip select is asserted or the DRAM block is selected using the specifications
programmed in the respective configuration register. Otherwise, the following occurs:
Table 10-3 shows the type of access as a function of match in the CSCRs and DACRs.
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access
• Chip-select control registers (CSCRn) provide port size and burst capability
• If the address and attributes do not match in CSCR or DACR, the MCF5307 runs an
• Should an address and attribute match in multiple CSCRs, the matching chip-select
• Should an address and attribute match both DACRs or a DACR and a CSCR, the
0
1
Multiple
0
1
Multiple
0
1
Multiple
control. See Section 10.4.1.2, “Chip-Select Mask Registers (CSMR0–CSMR7).”
indication, wait-state generation, and automatic acknowledge generation features.
See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).”
external burst-inhibited bus cycle with a default of external termination on a 32-bit
port.
signals are driven; however, the MCF5307 runs an external burst-inhibited bus cycle
with external termination on a 32-bit port.
operation is undefined.
Number of CSCR Matches
Table 10-3. Accesses by Matches in CSCRs and DACRs
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 10. Chip-Select Module
0
0
0
1
1
1
Multiple
Multiple
Multiple
Number of DACR Matches
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External
Defined by CSCR
External, burst-inhibited, 32-bit
Defined by DACRs
Undefined
Undefined
Undefined
Undefined
Undefined
Type of Access
Chip-Select Operation
10-3