MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 416

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Operation of External Master Transfers
Table 18-10 describes the two-wire bus arbitration protocol transition conditions.
18-28
External
Present
Table 18-10. MCF5307 Two-Wire Bus Arbitration Protocol Transition Conditions
Implicit
Explicit
Master
Master
Master
Reset
State
Figure 18-29. MCF5307 Two-Wire Bus Arbitration Protocol State Diagram
Condition
Label
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
C5
D1
D2
D3
D4
D1
RSTI
N
A
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
2
3
Freescale Semiconductor, Inc.
External
Master
For More Information On This Product,
Software Watchdog
C3
C5
A3
Reset
Go to: www.freescale.com
MCF5307 User’s Manual
—
A
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
D2
D4
Explicit
Master
Reset
B1
D3
BG
—
—
N
A
N
A
A
A
A
N
N
N
N
N
A
A
A
A1
A2
C1
C2
C4
Request
Bus
—
—
—
—
—
—
—
—
—
—
—
—
—
N
N
A
A
B2
B4
A4
Implicit
Master
Transfer in
Progress
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
A
B3
End of
Cycle
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
1
Implicit mas
Explicit mas
Implicit mas
Explicit mas
Explicit mas
Explicit mas
Explicit mas
Explicit mas
Implicit mas
Explicit mas
EM mas
State
Next
Reset
Reset
EM
EM
EM
EM
4