MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 391
![IC MPU 32BIT COLDF 90MHZ 208FQFP](/photos/12/43/124330/mcf5307ai90b_sml.jpg)
MCF5307AI90B
Manufacturer Part Number
MCF5307AI90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307AI90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Maximum Clock Frequency
90 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
90MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
FQFP
Program Memory Size
8KB
Cpu Speed
90MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307AI90B
Manufacturer:
FREESCAL
Quantity:
153
Company:
Part Number:
MCF5307AI90B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5307AI90B
Manufacturer:
FREESCALE
Quantity:
20 000
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18.4 Data Transfer Operation
Data transfers between the MCF5307 and other devices involve the following signals:
The address bus, write data, TS, and all attribute signals change on the rising edge of
BCLKO. Read data is latched into the MCF5307 on the rising edge of BCLKO. AS, CSx,
OE, and BE/BWE change on the falling edge.
The MCF5307 bus supports byte, word, and longword operand transfers and allows
accesses to 8-, 16-, and 32-bit data ports. Transfer parameters such as port size, the number
of wait states for the external slave being accessed, and whether internal transfer
termination is enabled, can be programmed in the chip-select control registers (CSCRs) and
DRAM control registers (DACRs).
For aligned transfers larger than the port size, SIZ[1:0] behaves as follows:
Table 18-2 shows encoding for SIZ[1:0].
Figure 18-2 shows the byte lanes that external memory should be connected to and the
sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit
memory should be connected to D[31:24] (BE0). A longword transfer takes four transfers
on D[31:24], starting with the MSB and going to the LSB.
• Address bus (A[31:0])
• Data bus (D[31:0])
• Control signals (TS and TA)
• AS, CSx, OE, BE/BWE
• Attribute signals (R/W, SIZ, TT, TM, and TIP)
• If bursting is used, SIZ[1:0] stays at the size of transfer.
• If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows
the port size.
Freescale Semiconductor, Inc.
Table 18-2. Bus Cycle Size Encoding
For More Information On This Product,
00
01
10
11
Chapter 18. Bus Operation
SIZ[1:0]
Go to: www.freescale.com
Longword
Byte
Word
Line
Port Size
Data Transfer Operation
18-3
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