HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 12

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 4 Clock Pulse Generator....................................................................... 51
4.1
4.2
4.3
Section 5 Exception Processing......................................................................... 57
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Section 6 Interrupt Controller (INTC)............................................................... 73
6.1
6.2
6.3
Rev. 2.00, 09/04, page x of xl
Oscillator........................................................................................................................... 52
4.1.1
4.1.2
Function for Detecting the Oscillator Halt........................................................................ 54
Usage Notes ...................................................................................................................... 55
4.3.1
4.3.2
Overview........................................................................................................................... 57
5.1.1
5.1.2
5.1.3
Resets................................................................................................................................ 61
5.2.1
5.2.2
5.2.3
Address Errors .................................................................................................................. 63
5.3.1
5.3.2
Interrupts........................................................................................................................... 65
5.4.1
5.4.2
5.4.3
Exceptions Triggered by Instructions ............................................................................... 67
5.5.1
5.5.2
5.5.3
5.5.4
Cases when Exception Sources Are Not Accepted........................................................... 69
5.6.1
5.6.2
Stack Status after Exception Processing Ends .................................................................. 70
Usage Notes ...................................................................................................................... 71
5.8.1
5.8.2
5.8.3
Features............................................................................................................................. 73
Input/Output Pins.............................................................................................................. 75
Register Descriptions........................................................................................................ 75
Connecting a Crystal Resonator........................................................................... 52
External Clock Input Method .............................................................................. 53
Note on Crystal Resonator................................................................................... 55
Notes on Board Design ........................................................................................ 55
Types of Exception Processing and Priority ........................................................ 57
Exception Processing Operations ........................................................................ 58
Exception Processing Vector Table ..................................................................... 59
Types of Reset ..................................................................................................... 61
Power-On Reset ................................................................................................... 61
Manual Reset ....................................................................................................... 62
The Cause of Address Error Exception................................................................ 63
Address Error Exception Processing ................................................................... 64
Interrupt Sources.................................................................................................. 65
Interrupt Priority Level ........................................................................................ 66
Interrupt Exception Processing ............................................................................ 66
Types of Exceptions Triggered by Instructions ................................................... 67
Trap Instructions.................................................................................................. 67
Illegal Slot Instructions........................................................................................ 68
General Illegal Instructions.................................................................................. 68
Immediately after a Delayed Branch Instruction ................................................. 69
Immediately after an Interrupt-Disabled Instruction............................................ 69
Value of Stack Pointer (SP) ................................................................................. 71
Value of Vector Base Register (VBR)................................................................. 71
Address Errors Caused by Stacking of Address Error Exception Processing...... 71