HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 606

IC SUPERH MCU FLASH 256K 100QFP

HD64F7047F50

Manufacturer Part Number
HD64F7047F50
Description
IC SUPERH MCU FLASH 256K 100QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047F50

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Figure 19.8 shows a sample procedure for flash memory block area overlapping.
1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range H'FFFFD000 to
2. The flash memory area to be overlapped is selected by RAMER from a 4-kbyte area of the
3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM
4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash
5. A RAM area cannot be erased by execution of software in accordance with the erase
6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
Rev. 2.00, 09/04, page 564 of 720
H'FFFFDFFF.
EB0 to EB7 blocks.
addresses.
memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1
does not cause a transition to program mode or erase mode.
algorithm.
is needed in the overlapped RAM.
H'3FFFF
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
Figure 19.8 Example of RAM Overlap Operation (RAM[2:0] = b'000)
Flash Memory
EB8 to EB11
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
This area can be accessed from
both the flash memory addresses
and RAM addresses.
On-chip RAM
H'FFFFD000
H'FFFFDFFF
H'FFFFFFFF

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