HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 501

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3.21 Input Capture Registers 0 and 1 (ICR0, ICR1)
ICR0 and ICR1 are 16-bit readable/writable (word-access only) registers. The initial values are
H'0000. (These registers are abbreviated to ICR0 and ICR1 in this section.)
ICR0: ICR0 can be used for a global synchronization purpose. The timer value is captured at the
point specified by bit 13 in the timer control register (TCR) as long as it is enabled by bit 14 in
TCR, regardless of whether or not the received message matches the identifiers set in the receive
mailboxes. If it is disabled by bit 14 in TCR, ICR0 holds the current value.
ICR1: ICR1 is used to record the timestamp for messages to be transmitted and received. Bit 13 in
TCR controls at which point the timestamp should be recorded. The difference between ICR1 and
ICR0 is that ICR1 cannot be disabled so the timestamps recorded on messages are always
accurate.
15.3.22 Timer Compare Match Registers 0 and 1 (TCMR0 and TCMR1)
TCMR0 and TCMR1 are 16-bit readable/writable registers. It allows generation of the interrupt
signal and clearing of the timer values (TCMR0 only). TCMR0 and TCMR1 have entirely the
same function (except timer clearing).
Interrupt: The interrupt from each of TCMR1 and TCMR0 is flagged in bits 15 and 14 in IRR
just in such order. These flags cannot be masked (on generation of a compare match) but
generation of the interrupt signal can be masked by setting the IMR15 and IMR14 bits. If TCMR
is set to H′0000, no compare match will be generated. If a compare match is generated, bit 2 (or
bit 1) in TSR (timer status register) will also be set. If the IRR15 bit (or IRR14 bit) is set and the
IRR bit is cleared, the corresponding TSR bit will also be cleared.
Timer Clearing and Setting: The timer value can only be cleared by TCMR0 and set by LOSR.
If a compare match is generated when bit 11 in TCR is set, the timer value will be cleared.
TCMR1 have no such function.
Bit
15 to 0 TCMRn[15]
Bit Name
to TCMRn[0]
(n = 0 and 1)
Initial
Value
All 0
R/W
R/W
Description
Timer Compare Match Register (TCMRn)
TCMR0 and TCMR1 generate the interrupt signal by a
compare match with the timer (TCNTR). TCMR0 allows
interrupts and timer values to be cleared.
Rev. 2.00, 09/04, page 459 of 720