HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 141

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Note:
Bit
5
4
3
2
1
0
*
Bit Name
ID1
ID0
RW1
RW0
SZ1
SZ0
When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are
considered to be accessed in word-size (even when there are instructions in on-chip
memory and two instruction fetches are performed simultaneously in one bus cycle).
Operand size is word for instructions or determined by the operand size specified for
the CPU/DTC data access. It is not determined by the bus width of the space being
accessed.
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Instruction Fetch/Data Access Select1 and 0
These bits select whether to break on instruction fetch
and/or data access cycles.
00: No user break interrupt occurs
01: Break on instruction fetch cycles
10: Break on data access cycles
11: Break on both instruction fetch and data access
Read/Write Select 1 and 0
These bits select whether to break on read and/or write
cycles
00: No user break interrupt occurs
01: Break on read cycles
10: Break on write cycles
11: Break on both read and write cycles
Operand Size Select 1 and 0*
These bits select operand size as a break condition.
00: Operand size is not a break condition
01: Break on byte access
10: Break on word access
11: Break on longword access
cycles
Rev. 2.00, 09/04, page 99 of 720