HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 85

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on
reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is
entered. When the HSTBY pin is driven high and the RES pin level goes low, the power-on reset
state is entered.
Exception Processing State: The exception processing state is a transient state that occurs when
exception processing sources such as resets or interrupts alter the CPU’s processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception processing vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception processing vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
Program Execution State: In the program execution state, the CPU sequentially executes the
program.
Power-Down State: In the power-down state, the CPU operation halts and power consumption
declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode.
If the HSTBY pin is driven low when the RES pin is low, the CPU will enter the hardware
standby mode.
Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device
that has requested them.
Rev. 2.00, 09/04, page 43 of 720