HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 498

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 456 of 720
Bit
12
11
10
9
8 to 6
Bit Name
TCR12
TCR11
TCR10
TCR9
—
Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
Timestamp Control for Transmission
Specifies if the timestamp operates in corresponding
TXPR bit or TXACK bit. Use ICR1 for timestamp in
transmission.
0: Timestamp in TXPR bit
1: Timestamp in TXACK bit
Timer Clear/Set Control by TCMR0
Specifies if the timer is to be cleared and set to LOSR
when TCMR0 matches TCNTR.
Note: TCMR0 is capable of generating an interrupt
0: Timer is not cleared by TCMR0
1: Timer is cleared and set to LOSR by TCMR0
Timer Clear/Set Control by CCM
Specifies if the timer is to be cleared and set to LOSR by
CAN-ID compare match (CCM) when a mailbox receives
a message, only when the CCM bit of the corresponding
mailbox and this bit are both set.
Note: CCM cannot generate an interrupt signal. This
0: Timer cannot be cleared by CCM
1: Timer is cleared by CCM and set to LOSR
ICR0 Automatic Disable by CCM
Specifies if ICR0 is to be disabled by CAN-ID compare
match (CCM) when a mailbox stores a receive message.
When a mailbox stores a receive message, TCR14 (bit
14) of this register is automatically cleared and the ICR0
value is retained, only if the CCM bit of the
corresponding mailbox and this bit are both set.
0: TCR14 is not cleared
1: TCR14 is automatically cleared
Reserved
These bits are always read as 0. The write value should
always be 0.
signal to the host processor via IRR14.
can be performed by IRR1 or IRR2.