HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 751

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Item
15.1 Features
15.2 Input/Output Pins
15.3 Register Descriptions 410
15.3.1 Master Control
Register (MCR)
15.3.1 Master Control
Register (MCR)
Page
407,
408
409
410
410
413 to
418
414
415
Revisions (See Manual for Details)
Deleted
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•
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Timer: . . . Two compare match registers generate the
interrupt signal to clear the counter values and set the local
offset registers.
When using HCAN2 pins, settings must be made in HCAN2
configuration mode.
A Renesas HA13721 compatible model is recommended.
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•
•
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HCAN → HCAN2
Bit 11:
Disable Error Counters
Enables/disables the error counters (TEC/REC) to be
functional. When this bit is enabled, the error counters
(TEC/REC) remain unchanged and holds the current value.
When this bit is disabled, the error counters (TEC/REC)
function according to the CAN specification.
Bit 8:
Enable Internal Loop
Enables/disables the internal TX looped back to the internal
Rx. Deleted
0: Rx is fed from the Rx Pin
Communication speed: Max. 1 Mbps
HCAN2 halt mode
Other feature
The DTC can be activated by message receive mailbox
(HCAN2 mailbox 0 only)
Module standby mode can be set
Read section 15.8, Usage Notes.
Transmit wait registers (TXPR1, TXPR0)
Transmit wait cancel registers (TXCR1, TXCR0)
Transmit acknowledge registers (TXACK1, TXACK0)
Abort acknowledge registers (ABACK1, ABACK0)
Receive complete registers (RXPR1, RXPR0)
Remote request registers (RFPR1, RFPR0)
Mailbox interrupt mask registers (MBIMR1, MBIMR0)
Unread message status registers (UMSR1, UMSR0)
:
Rev. 2.00, 09/04, page 709 of 720