HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 288

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Complementary PWM Mode Output Protection Function: Complementary PWM mode output
has the following protection functions.
1. Register and counter miswrite prevention function
2. Halting of PWM output by external signal
3. Halting of PWM output when oscillator is stopped
Rev. 2.00, 09/04, page 246 of 720
With the exception of the buffer registers, which can be rewritten at any time, access by the
CPU can be enabled or disabled for the mode registers, control registers, compare registers,
and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus
control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total
21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4;
TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and
TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function
enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to
the mode registers, control register, and counters. In access disabled state, an undefined value
is read from the registers concerned, and cannot be modified.
The 6-phase PWM output pins can be set automatically to the high-impedance state by
inputting specified external signals. There are four external signal input pins.
See section 10.9, Port Output Enable (POE), for details.
If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins
automatically go to the high-impedance state. The pin states are not guaranteed when the clock
is restarted.
See section 4.2, Function for Detecting the Oscillator Halt, for details.