HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 397

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4.4
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below. When the operating mode, transfer format, etc., is changed,
the TE and RE bits must be cleared to 0 before making the change using the following procedure.
When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does
not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When the external clock is used in asynchronous mode, the clock must be supplied even during
initialization.
Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1
SCI initialization (Asynchronous mode)
Set RIE, TIE, TEIE, and MPIE bits
simultaneously.
Set CKE1 and CKE0 bits in SCR
Set PFC of the external pin used
Set TE and RE bits in SCR to 1
Clear RIE, TIE, TEIE, MPIE,*
TE and RE bits in SCR to 0
< Initialization completion>
Set data transfer format in
(TE and RE bits are 0)
1-bit interval elapsed?
Start transmission
Set value in BRR
SCK, TxD, RxD
Figure 12.5 Sample SCI Initialization Flowchart
SMR
Yes
Wait
No
[1]
[2]
[3]
[4]
[5]
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR
[3] Write a value corresponding to the
[4] Set PFC of the external pin used.
[5] Wait at least one bit interval, then
and SCMR.
bit rate to BRR. Not necessary if an
external clock is used.
Set RxD input during receiving and
TxD output during transmitting. Set
SCK input/output according to
contents set by CKE1 and CKE0.
When CKE1 and CKE0 are 0 in
asynchronous mode, setting the
SCK pin is unnecessary.
Outputting clocks from the SCK pin
starts at synchronous clock output
setting.
set the TE bit or RE bit in SCR to
1.* At this time, the TxD, RxD, and
SCK pins can be used. The TxD
pin is in a mark state during
transmitting, and RxD pin is in an
idle state for waiting the start bit
during receiving.
Rev. 2.00, 09/04, page 355 of 720