HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 640

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

occur). Note that the compared address is the previous fully output address, and not an interrupted
address (since the upper address of an interrupted address will be unknown).
The interval from the start of execution at the branch destination address in the PC until the
AUDATA pins output 10xx is 1.5 or 2 AUDCK cycles.
23.4
23.4.1
In this mode, all the modules connected to this LSI's internal or external bus can be read and
written to, allowing RAM monitoring and tuning to be carried out.
When an address is written to AUDATA externally, the data corresponding to that address is
output. If an address and data are written to AUDATA, the data is transferred to the address.
Rev. 2.00, 09/04, page 598 of 720
AUDCK
AUDSYNC
AUDATA [3:0]
AUDCK
AUDSYNC
AUDATA [3:0]
Start of execution at branch destination address in PC (1)
RAM Monitor Mode
Overview
Start of execution at branch destination address in PC
0011
0011
Figure 23.3 Example of Output in Case of Successive Branches
Figure 23.2 Example of Data Output (32-Bit Output)
0011
0011
Start of execution at branch destination address in PC (2)
1011
1011
A3 to A0 A7 to A4 A11 to A8 A15 to A12 A19 to A16 A23 to A20 A27 to A24 A31 to A28
A3 to A0 A7 to A4
1010
A3 to A0
A7 to A4 A11 to A8 A15 to A12
0011
0011
0011