HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 487

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

• UMSR0
15.3.16 Mailboxes (MB0 to MB31)
Mailboxes play a role as message buffers to transmit/receive CAN frames. Each mailbox is
comprised of four identical storage fields (message control, message data, timestamp, and local
acceptance filter mask (LAFM)). The 32 mailboxes are available for the HCAN2.
The following table shows the address map for the control, data, timestamp, and LAFM/TTT
addresses for each mailbox.
Notes: 1. Since mailboxes are in RAM, their initial values after a power-on are undefined. Be
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2. Set the mailbox configuration (MBC) bits of unused mailboxes to B'111, and no access
3. Only word access can be used in message control, timestamp, LAFM field. Word/bytes
4. When a message is received in the mailbox where the LAFM is enabled, set ID
Bit Name
UMSR15
UMSR14
UMSR13
UMSR12
UMSR11
UMSR10
UMSR9
UMSR8
UMSR7
UMSR6
UMSR5
UMSR4
UMSR3
UMSR2
UMSR1
UMSR0
sure to initialize them by writing 0 or 1.
is recommended.
access can be used in message data area.
(including EXT-ID when it is enabled) will be overwritten to the ID (EXT-ID) values
of received messages.
Initial Value R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Unread receive message is overwritten by a new
message
[Setting condition]
•
[Clearing condition]
•
Note: Writing operation by the CPU is valid only for
When a new message is received before RXPR
is cleared
Writing 1
clearing condition (writing 1) of set status.
Rev. 2.00, 09/04, page 445 of 720