HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 538

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PWM Output Active Level Setting: In the operating modes, the active level of PWM pulses is
set with bits OLSN and OLSP in the timer mode register (TMDR).
The output level can be set for the three positive phases and the three negative phases of 6-phase
output. The operating mode must be exited before setting or changing the output level.
Dead Time Setting: In the operating modes, PWM pulses are output with a non-overlap
relationship between the positive and negative phases. This non-overlap time is known as the dead
time. The non-overlap time is set in the timer dead time data register (TDDR). The dead time
generation waveform is generated by comparing the value set in TDDR with the timer dead time
counters (TDCNT) for each phase. The operating mode must be exited before changing the
contents of TDDR.
PWM Period Setting: In the operating modes, 1/2 the PWM pulse period is set in the TPBR
register. The TPBR value should always be set in the range H'0000 to H'FFFF – 4Td. The value
set in TPBR is transferred to TPDR at the timing selected with bits MD1 and MD0 in the timer
mode register (TMDR). After the transfer, the value in TPDR is {TPBR value + 2Td}.
The new PWM period is effective from the next period when data is updated at the TCNT counter
crest, and from the same period when data is updated at the trough.
Register Updating: In the operating modes, buffer registers are used to update compare register
data. Update data can be written to a buffer register at all times. The buffer register value is
transferred to the compare register at the timing set by bits MD1 and MD0 in the timer mode
register (TMDR) (except in the case of a write to the free operation address for TBRU to TBRW,
in which case the value is transferred to the corresponding compare register immediately).
Initial Output in Operating Modes: The initial output in the operating modes is determined by
the initial values of TBRU to TBRW.
Table 16.2 shows the relationship between the initial value of TBRU to TBRW and the initial
output.
Table 16.2 Initial Values of TBRU to TBRW and Initial Output
Rev. 2.00, 09/04, page 496 of 720
Initial Value of TBRU to TBRW
TBR = H'0000
H'0000 < TBR ≤ Td
Td < TBR ≤ H'FFFF – 2Td
OLSP = 1, OLSN = 1
Positive phase: 1
Negative phase: 0
Positive phase: 0
Negative phase: 0
Positive phase: 0
Negative phase: 1
Initial Output
OLSP = 0, OLSN = 0
Positive phase: 0
Negative phase: 1
Positive phase: 1
Negative phase: 1
Positive phase: 1
Negative phase: 0