HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 177

IC SUPERH MCU FLASH 256K 100QFP

HD64F7047F50

Manufacturer Part Number
HD64F7047F50
Description
IC SUPERH MCU FLASH 256K 100QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047F50

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7047F50
Manufacturer:
RENESAS
Quantity:
4 000
Part Number:
HD64F7047F50MV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7047F50V
Manufacturer:
PANJIT
Quantity:
30 000
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS
Quantity:
386
Part Number:
HD64F7047F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7047F50V
Quantity:
2 070
9.2
Table 9.1 shows the bus state controller pin configuration.
Table 9.1
9.3
The BSC has four registers. For details on these register addresses and register states in each
processing states, refer to appendix A, Internal I/O Register.
These registers are used to control wait states, bus width, and interfaces with memories like ROM
and SRAM. All registers are 16 bits.
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Wait control register 1 (WCR1)
• RAM emulation register (RAMER)
Name
Address bus
Data bus
Chip select
Read
Lower write
Wait
Bus request
Bus acknowledge
Input/Output Pin
Register Configuration
Pin Configuration
Abbr.
A17 to A0
D7 to D0
CS0
RD
WRL
WAIT
BREQ
BACK
I/O
O
I/O
O
O
O
I
I
O
Description
Address output
8-bit data bus
Chip select signal indicating the area being
accessed
Strobe that indicates the read cycle
Strobe that indicates a write cycle to the lower 8
bits (D7 to D0)
Wait state request signal
Bus release request input
Bus use enable output
Rev. 2.00, 09/04, page 135 of 720

Related parts for HD64F7047F50