HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 608

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 566 of 720
* Use a t
Note
Number of Writes n
*
Notes:
6: Write Pulse Width
Reprogram Data Computation Table
1000
Wait (tsp10, tsp30, or tsp200) µs
998
999
Write pulse application subroutine
10
11
12
13
sp
1
2
3
4
5
6
7
8
9
Original Data
Clear PSU bit in FLMCR1
10 write pulse for additional programming.
Reprogram data storage
Additional-programming
Set PSU bit in FLMCR1
Clear P bit in FLMCR1
Program data storage
*
*
*
*
*
Set P bit in FLMCR1
1 Data transfer is performed by byte transfer. The lower 8 bits of the start address to be written to must be H'00 or H'80.
2 Verify data is read in 32-bit (longword) units.
3 Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
4 A 128-byte area for the storage of programming data, a 128-byte area for the storage of reprogramming data, and a 128-byte area for the storage of additional-
5 A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See note 6 for details of the pulse widths. When writing of
(D)
data storage area
Apply Write Pulse
area (128 bytes)
area (128 bytes)
0
0
1
1
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the subsequent verify operation ends in failure.
programming data must be provided in RAM. The contents of the reprogram data area and additional-program data area are modified as programming proceeds.
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Wait (t
Wait (t
(128 bytes)
Disable WDT
Enable WDT
Wait (t
End Sub
RAM
spsu
cpsu
Write Time (tsp) µs
cp
Verify Data
) µs
) µs
) µs
t
t
t
t
t
t
t
t
t
t
(V)
t
t
t
t
t
t
sp
sp
sp
sp
sp
sp
sp
sp
sp
sp
0
1
0
1
sp
sp
sp
sp
sp
sp
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
Figure 19.9 Program/Program-Verify Flowchart
Reprogram Data
Increment address
*
*
*
*
(X)
Start of programming
End of programming
7
5
7
7
1
0
1
1
*
7
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Apply Write Pulse (tsp10) (Additional programming)
Successively write 128-byte data from reprogram
data area in RAM to flash memory
NG
Transfer reprogram data to reprogram data area
Comments
Additional-programming data computation
Store 128-byte program data in program
Transfer additional-programming data to
data area and reprogram data area
Apply
H'FF dummy write to verify address
additional-programming data area
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Start of programming
Set PV bit in FLMCR1
Write Pulse (tsp30 or tsp200)
End of programming
Wait (t
Wait (t
Read verify data
Wait (t
Wait (t
Wait (t
Write data =
verify data?
OK
OK
OK
128-byte
START
m = 0 ?
m = 0
6 ≥ n ?
6
n = 1
sswe
cswe
≥
spvr
cpv
spv
Additional-Programming Data Computation Table
n?
Reprogram Data
Sub-Routine-Call
OK
OK
Sub-Routine-Call
) µs
) µs
) µs
) µs
) µs
(X')
0
0
1
1
NG
NG
NG
Verify Data
*
*
*
*
NG
*
*
See note
7
7
7
2
(V)
3
7
0
1
0
1
*
*
4
*
1
1
m = 1
*
*
*
4
4
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Clear SWE bit in FLMCR1
6 for pulse width
Programming Data (Y)
Programming failure
Wait (t
Additional-
n ≥ N?
0
1
1
1
cswe
OK
) µs
*
7
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
NG
n ← n + 1
Comments
*
Reprogram
7