HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 500

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3.20 Local Offset Register (LOSR)
LOSR is a 16-bit readable/writable register. The purpose of this register is to set a local offset to
the timer counter (TCNTR). Whenever TCNTR is cleared by overflow, timer compare match, or
CAN-ID compare match, TCNTR starts counting from the value set in this register.
Rev. 2.00, 09/04, page 458 of 720
Bit
1
0
Bit
15 to 0 LOSR15 to
Bit Name
TSR1
TSR0
Bit Name
LOSR0
Initial
Value
0
0
Initial
Value
All 0
R/W
R
R
R/W
R/W
Description
Compare Match Flag 0
Indicates that a compare-match condition occurred in
compare match register 0 (TCMR0). When the value set
in TCMR0 matches the timer value (TCMR0 = TCNTR),
this bit is set.
Note: This bit is not set if the TCMR0 value is H'0000.
0: Timer compare match has not occurred
1: Timer compare match has occurred (TCMR0)
[Clearing condition]
•
[Setting condition]
•
Timer Overflow Flag
Indicates that the timer has overflowed and is reset to
H'0000.
0: Timer has not overflowed
1: Timer has overflowed
[Clearing condition]
•
[Setting condition]
•
Description
Local Offset Register
When the timer counter (TCNTR) is cleared by overflow,
timer compare match, or CAN-ID compare match, TCNTR
starts counting from the value set in LOSR.
Writing 1 to IRR14
TCMR0 = TCNTR
Writing 1 to IRR13
When the timer value changes from H'FFFF to H'0000
Also, this bit is read-only and is cleared when
IRR14 (timer compare match interrupt flag 0) is
cleared.