HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 190

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.10
On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 9.3.
Table 9.3
Notes: 1. Converted to the peripheral clock.
9.11
1. One bus cycle:
9.12
In this LSI, two words (equivalent to two instructions) are normally fetched in a single instruction
fetch. This is also true when the program is located in external memory, irrespective of whether
the external memory bus width is 8 or 16 bits.
If the program counter value immediately after the program branched is an odd-word (2n+1)
address, or if the program counter value immediately before the program branches is an even-word
(2n) address, the CPU will always fetch 32 bits (equivalent to two instructions) that include the
respective word instruction.
Rev. 2.00, 09/04, page 148 of 720
On-chip
Peripheral
Module
Connected
bus width
Access
cycle
The bus is never released during a single bus cycle. For example, in the case of a longword
read (or write) in 8-bit normal space, the four memory accesses to the 8-bit normal space
constitute a single bus cycle, and the bus is never released during this period. Assuming that
one memory access requires two states, the bus is not released during an 8-state period.
2. Converted to the system clock.
On-chip Peripheral I/O Register Access
Cycles in which Bus is not Released
CPU Operation when Program is In External Memory
SCI
8bit
2cyc
*
On-chip Peripheral I/O Register Access
1
MTU,
POE
16bit 16bit 16bit
2cyc
*
1
INTC
2cyc
*
2
8 bit
PFC,
PORT CMT A/D
2cyc
*
2
Figure 9.10 One Bus Cycle
16bit 16bit 16bit 16bit 16bit 16bit 16bit
2cyc
*
Bus is not Released
8 bit
1
Cycles in which
2cyc
*
1
8 bit
UBC WDT DTC MMT HCAN2 H-UDI
3cyc
*
2
3cyc
*
2
8 bit
3cyc
*
2
2cyc
*
1
8cyc
*
2
16bit
2cyc
*
1