HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 261

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 10.30 shows an example
of procedure for selecting the reset synchronized PWM mode.
1. Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-
2. Set bits TPSC2–TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and
3. When performing brushless DC motor control, set bit BDC in the timer gate control register
4. Reset TCNT_3 and TCNT_4 to H'0000.
5. TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition
6. Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE
7. Set bits MD3–MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode.
8. Set the enabling/disabling of the PWM waveform output pin in TOER.
9. Set the CST3 bit in the TSTR to 1 to start the count operation.
Notes: 1. The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X
synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted.
clock edge for channel 3. Set bits CCLR2–CCLR0 in the TCR_3 to select TGRA compare-
match as a counter clear source.
(TGCR) and set the feedback signal input source and output chopping or gate signal direct
output.
timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within
the compare-match range of TCNT_3.
X ≤ TGRA_3 (X: set value).
in the timer output control register (TOCR), and set the PWM output level with bits OLSP and
OLSN.
TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C and TIOC4D function as PWM
output pins*. Do not set to TMDR_4.
* PFC registers should be specified before this procedure.
by setting X = TGRA, i.e., cycle = duty.
Rev. 2.00, 09/04, page 219 of 720