HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 450

IC SUPERH MCU FLASH 256K 100QFP

HD64F7047F50

Manufacturer Part Number
HD64F7047F50
Description
IC SUPERH MCU FLASH 256K 100QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047F50

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7047F50
Manufacturer:
RENESAS
Quantity:
4 000
Part Number:
HD64F7047F50MV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7047F50V
Manufacturer:
PANJIT
Quantity:
30 000
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS
Quantity:
386
Part Number:
HD64F7047F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7047F50V
Quantity:
2 070
• Other feature
• Module standby mode can be set
• Read section 15.8, Usage Notes.
Microprocessor Interface (MPI): The MPI allows communication between the CPU and
HCAN2’s registers/mailboxes to control the timer unit and memory interface. It also contains the
wakeup control logic that detects the CAN bus activities and notifies to the MPI and other parts of
the HCAN2 so that the HCAN2 can automatically exit HCAN2 sleep mode.
Mailbox (MB): The mailbox is essentially arrayed on the RAM as message buffers. There are 32
mailboxes, and each mailbox has the following information.
• CAN message control
Rev. 2.00, 09/04, page 408 of 720
The DTC can be activated by message receive mailbox (HCAN2 mailbox 0 only)
CAN interface
TCNTR
BCR
MCR
GSR
TCR
TSR
Microprocessor
interface (MPI)
16-bit timer
Figure 15.1 HCAN2 Block Diagram
TCMR
LOSR
ICR
IMR
IRR
REC
Transmit buffer
HRxD1
Receive buffer
HTxD1
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailboxes 0 to 31 (RAM)
• Message control
• Message data
• LAFM/Tx-trigger time
MBIMR
TXCR
RXPR
TXPR
TEC
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
Mailbox control
Mailbox16
Mailbox17
Mailbox18
Mailbox19
Mailbox20
Mailbox21
Mailbox22
Mailbox23
ABACK
TXACK
UMSR
RFPR
Mailbox24
Mailbox25
Mailbox26
Mailbox27
Mailbox28
Mailbox29
Mailbox30
Mailbox31

Related parts for HD64F7047F50