HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 398

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4.5
Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
Figure 12.7 shows a sample flowchart for transmission in asynchronous mode.
Rev. 2.00, 09/04, page 356 of 720
TxD
TDRE
TEND
written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request
(TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR
before transmission of the current transmit data has finished, continuous transmission can be
enabled.
multiprocessor bit (may be omitted depending on the format), and stop bit.
serial transmission of the next frame is started.
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
TXI interrupt
request
generated
Figure 12.6 Example of Operation in Transmission in Asynchronous Mode
1
Data transmission (Asynchronous mode)
Start
bit
0
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
D0
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
frame
Data
D7
Parity
bit
0/1
TXI interrupt
request
generated
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
0/1
TEI interrupt
request
generated
Stop
bit
1
Idle state
(mark state)
1