HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 649

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

24.2.1
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Bit
7
6
5
4 to 1 
0
Bit Name
SSBY
HIZ

IRQEL
Standby Control Register (SBYCR)
Initial
Value
0
0
0
All 1
1
R/W
R/W
R/W
R
R
R/W
Port High-Impedance
Description
Software Standby
This bit specifies the transition mode after executing the
SLEEP instruction.
0: Shifts to sleep mode after the SLEEP instruction has
1: Shifts to software standby mode after the SLEEP
This bit cannot be set to 1 when the watchdog timer
(WDT) is operating (when the TME bit in TCSR of the
WDT is set to 1). When transferring to software standby
mode, clear the TME bit to 0, stop the WDT, then set the
SSBY bit to 1.
In software standby mode, this bit selects whether the pin
state of the I/O port is retained or changed to high-
impedance.
0: In software standby mode, the pin state is retained.
1: In software standby mode, the pin state is changed to
The HIZ bit cannot be set to 1 when the TEM bit in TCSR
of the WDT is set to 1.
When changing the pin state of the I/O port to high-
impedance, clear the TEM bit to 0, then set the HIZ bit to
1.
Reserved
This bit is always read as 0, and should always be written
with 0.
Reserved
These bits are always read as 1, and should always be
written with 1.
IRQ3 to IRQ0 Enable
IRQ interrupts are enabled to clear software standby
mode.
0: Software standby mode is cleared.
1: Software standby mode is not cleared.
been executed
instruction has been executed
high-impedance.
Rev. 2.00, 09/04, page 607 of 720