HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 155

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

[Legend]
X: Don’t care
Bit
7
6
5
4
3 to 0
Bit Name
DTS
CHNE
DISEL
NMIM

Undefined
Undefined
Undefined
Initial
Value
Undefined
Undefined
R/W





Description
DTC Transfer Mode Select
Specifies whether the source or the destination is set
to be a repeat area or block area, in repeat mode or
block transfer mode.
0: Destination is repeat area or block area
1: Source is repeat area or block area
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed.
0: Chain transfer is canceled
1: Chain transfer is set
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the activation source flag, and clearing of DTER is
not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated for every DTC transfer. When this bit is set
to 0, a CPU interrupt request is generated at the time
when the specified number of data transfer ends.
DTC NMI Mode
This bit designates whether to terminate transfers
when an NMI is input during DTC transfers.
0: Terminate DTC transfer upon an NMI
1: Continue DTC transfer until end of transfer being
Reserved
These bits have no effect on DTC operation and
should always be written with 0.
executed
Rev. 2.00, 09/04, page 113 of 720