HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 180

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.5
9.5.1
BCR1 is a 16-bit readable/writable register that enables access to the MMT and MTU control
registers and specifies the bus size of the CS0 space.
The AOSZ bit of BCR1 is written to during the initialization stage after a power-on reset. Do not
change the values thereafter. In on-chip ROM enabled mode, do not access any of the CS0 space
until completion of register initialization.
Rev. 2.00, 09/04, page 138 of 720
Bit
15
14
13
12 to 8
7 to 4
3 to 1
0
Description of Registers
Bus Control Register 1 (BCR1)
Bit Name

MMTRWE 1
MTURWE



A0SZ
Initial
Value
0
1
All 0
All 0
All 1
1
R/W
R
R/W
R/W
R
R
R
R/W
Description
Reserved
This bit is always read as 0 and should always be
written with 0.
MMT Read/Write Enable
This bit enables MMT control register access. For
details, refer to MMT section.
0: MMT control register access is disabled
1: MMT control register access is enabled
MTU Read/Write Enable
This bit enables MTU control register access. For
details, refer to MTU section.
0: MTU control register access is disabled
1: MTU control register access is enabled
Reserved
These bits are always read as 0 and should always
be written with 0.
Reserved
These bits are always read as 0 and should always
be written with 0.
Reserved
These bits are always read as 1 and should always
be written with 1.
In on-chip ROM enabled mode, 0 should be written to
this bit to specify a bus size of 8 bits before the CS0
space is accessed.
Note: In on-chip ROM disabled mode, the CS0
space bus size is specified by the mode pin.