HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 539

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PWM Output Generation in Operating Modes: In the operating modes, a 3-phase PWM
waveform is output with a non-overlap relationship between the positive and negative phases. This
non-overlap time is called the dead time.
The PWM waveform is generated from an output generation waveform generated by ANDing the
compare output waveform with the dead time generation waveform. Waveform generation for one
phase (the U-phase) is shown here. The V-phase and W-phase waveforms are generated in the
same way.
1. Compare Output Waveform
2. Dead Time Generation Waveform
3. Output Generation Waveform
4. PWM Waveform
The compare output waveform is generated by comparing the values in the TCNT counter and
the TGR registers.
For compare output waveform U phase A (CMOUA), 0 is output if TGRUU > TCNT in the T1
interval (when TCNT is counting up), and 1 is output if TGRUU ≤ TCNT. In the T2 interval
(when TCNT is counting down), 0 is output if TGRU > TCNT, and 1 is output if TGRU ≤
TCNT.
For compare output waveform U phase B (CMOUB), 1 is output if TGRU > TCNT in the T1
interval, and 0 is output if TGRU ≤ TCNT. In the T2 interval, 1 is output if TGRUD > TCNT,
and 0 is output if TGRUD ≤ TCNT.
For dead time generation waveform U phases A (DTGUA) and B (DTGUB), 1 is output as the
initial value.
TDCNT0 starts counting at the falling edge of CMOUA. DTGUA outputs 0 if TDCNT0 is
counting, and 1 otherwise.
TDCNT1 starts counting at the falling edge of CMOUB. DTGUB outputs 0 if TDCNT1 is
counting, and 1 otherwise.
Output generation waveform U phase A (OGUA) is generated by ANDing CMOUA and
DTGUB, and output generation waveform U phase B (OGUB) is generated by ANDing
CMOUB and DTGUA.
The PWM waveform is generated by converting the output generation waveform to the output
level set in bits OLSN and OLSP in the timer mode register (TMDR).
Figure 16.5 shows an example of PWM waveform generation (operating mode 3, OLSN = 1,
OLSP = 1).
Rev. 2.00, 09/04, page 497 of 720