HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 419

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.8
12.8.1
The TDRE bit in the serial status register (SSR) is a status flag indicating transferring of transmit
data from TDR into TSR. The SCI sets the TDRE bit to 1 when it transfers data from TDR to
TSR.
Data can be written to TDR regardless of the TDRE bit status.
If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost
because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure
to check that the TDRE bit is set to 1.
12.8.2
SCI operation can be disabled or enabled using the module standby control register. The initial
setting is for SCI operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 24, Power-Down Modes.
12.8.3
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
PER flag may also be set. Note that, since the SCI continues the receive operation after receiving
a break, even if the FER flag is cleared to 0, it will be set to 1 again.
12.8.4
The TxD pin becomes of the I/O port general I/O pin with the I/O direction and level determined
by the port data register (DR) and the port I/O register (IOR) of the pin function controller (PFC).
These conditions allow break signals to be sent.
The DR value is substituted for the marking status until the PFC is set. Consequently, the output
port is set to initially output a 1.
To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an
output port using the PFC.
When the TE bit is cleared to 0, the transmission section is initialized regardless of the present
transmission status.
Usage Notes
TDR Write and TDRE Flag
Module Standby Mode Setting
Break Detection and Processing (Asynchronous Mode Only)
Sending a Break Signal (Asynchronous Mode Only)
Rev. 2.00, 09/04, page 377 of 720