HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 66

IC SUPERH MCU FLASH 256K 100QFP

HD64F7047F50

Manufacturer Part Number
HD64F7047F50
Description
IC SUPERH MCU FLASH 256K 100QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047F50

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Rev. 2.00, 09/04, page 24 of 720
Addressing
Mode
Indirect register
addressing with
displacement
Indirect indexed
register
addressing
Indirect GBR
addressing with
displacement
Indirect indexed
GBR
addressing
Instruction
Format
@(disp:4,
Rn)
@(R0, Rn) The effective address is the sum of Rn and R0.
@(disp:8,
GBR)
@(R0,
GBR)
Effective Address Calculation
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
The effective address is the sum of GBR value and
an 8-bit displacement (disp). The value of disp is
zero-extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
The effective address is the sum of GBR value and
R0.
(zero-extended)
(zero-extended)
GBR
1/2/4
Rn
R0
R0
GBR
1/2/4
disp
disp
Rn
×
×
+
+
+
+
Rn + disp × 1/2/4
+ disp × 1/2/4
GBR + R0
Rn + R0
GBR
Equation
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Rn + R0
Byte:
GBR + disp
Word:
GBR + disp ×
2
Longword:
GBR + disp ×
4
GBR + R0

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