CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1007

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDRM[7:0]
RDRM[7:0]
Reset
Reset
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Field
24.0.5.29 Port M Reduced Drive Register (RDRM)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each Port M output pin as either full or reduced. If the
port is used as input this bit is ignored.
Field
24.0.5.30 Port M Pull Device Enable Register (PERM)
Read: Anytime.
Write: Anytime.
7–0
7–0
W
W
R
R
RDRM7
PERM7
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Reduced Drive Port M
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
7
0
7
0
on PTM or PTIM registers, when changing the DDRM register.
RDRM6
PERM6
Figure 24-32. Port M Pull Device Enable Register (PERM)
0
0
6
6
Figure 24-31. Port M Reduced Drive Register (RDRM)
Table 24-29. DDRM Field Descriptions
Table 24-30. RDRM Field Descriptions
RDRM5
PERM5
5
0
5
0
RDRM4
PERM4
0
0
4
4
Description
Description
RDRM3
PERM3
3
0
3
0
RDRM2
PERM2
0
0
2
2
RDRM1
PERM1
1
0
1
0
RDRM0
PERM0
0
0
0
0