CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 968

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-70
are displayed, a ‘mux’ indicates time-multiplexing between the two functions and an ‘or’ means that a
configuration bit exists which can be altered after reset to select the respective function (displayed in
italics). Refer to S12X_EBI section for details.
970
PC[7:0]
PD[7:0]
PK[6:4]
PK[3:0]
PB[7:1]
PA[7:0]
PK7
PB0
PE7
PE6
PE5
PE4
PE3
PE2
PJ5
PJ4
Pin
Normal Single-
lists the pin functions in relationship with the different operating modes. If two entries per pin
ECLKX2
ECLK
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Chip
or
or
Single-Chip Modes
Table 23-70. Expanded Bus Pin Functions versus Operating Modes
Special Single-
ECLKX2
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ECLK
GPIO
GPIO
GPIO
GPIO
GPIO
Chip
or
or
MC9S12XDP512 Data Sheet, Rev. 2.21
ADDR[22:20]
ADDR[19:16]
ADDR[15:8]
DATA[15:8]
Expanded
ADDR[7:1]
DATA[7:0]
ECLKX2
Normal
CS0
EWAIT
ECLK
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
UDS
LDS
CS2
WE
RE
or
or
or
or
or
or
or
or
or
or
or
or
(1)
ADDR[22:20]
ADDR[19:16]
Single-Chip
ADDR[15:8]
IQSTAT[3:0]
Emulation
DATA[15:8]
ADDR[7:1]
DATA[7:0]
IVD[15:8]
ACC[2:0]
ECLKX2
IVD[7:1]
ADDR0
TAGLO
LSTRB
TAGHI
ECLK
GPIO
GPIO
GPIO
IVD0
mux
mux
mux
mux
mux
R/W
Expanded Modes
ADDR[22:20]
ADDR[19:16]
IQSTAT[3:0]
ADDR[15:8]
DATA[15:8]
Emulation
Expanded
ADDR[7:1]
DATA[7:0]
IVD[15:8]
ACC[2:0]
ECLKX2
IVD[7:1]
ADDR0
TAGLO
LSTRB
EWAIT
CS0
TAGHI
ECLK
GPIO
GPIO
GPIO
IVD0
R/W
CS2
mux
mux
mux
mux
mux
or
or
or
(1)
Freescale Semiconductor
ADDR[22:20]
ADDR[19:16]
ADDR[15:8]
DATA[15:8]
ADDR[7:1]
DATA[7:0]
ECLKX2
Special
ADDR0
LSTRB
ECLK
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Test
R/W
CS2
CS0
or
or
or
or
or