CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1274

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix A Electrical Characteristics
In
In Master Mode the allowed maximum f
SPI Section) derates with increasing f
A.7.2
In
1276
f
SCK
Table A-26
Num
Figure A-9
10
11
12
13
1
1
2
3
4
5
6
9
/f
1/4
1/2
bus
C
D
D
D
D
D
D
D
D
D
D
D
D
Slave Mode
the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
the timing characteristics for master mode are listed.
Figure A-8.
SCK frequency
SCK period
Enable lead time
Enable lag time
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid after SCK edge
Data valid after SS fall (CPHA = 0)
Data hold time (outputs)
Rise and fall time inputs
Rise and fall time outputs
5
10
Derating of maximum f
Table A-26. SPI Master Mode Timing Characteristics
Characteristic
15
MC9S12XDP512 Data Sheet, Rev. 2.21
20
bus.
SCK
25
to f
bus
SCK
Symbol
30
ratio (= minimum Baud Rate Divisor, pls. see
t
t
t
f
t
wsck
t
t
lead
vsck
t
t
t
t
sck
sck
t
vss
lag
su
ho
rfo
hi
rfi
to f
bus
35
1/2048
Min
ratio in Master Mode
—
—
—
—
—
—
—
2
8
8
0
40
Typ
1/2
1/2
1/2
—
—
—
—
—
—
—
—
—
f
bus
Freescale Semiconductor
[MHz]
2048
Max
1 2
15
15
—
—
—
—
—
—
8
8
Unit
f
t
t
t
t
bus
bus
ns
ns
ns
ns
ns
ns
ns
sck
sck
sck